The instant application claims priority from European Patent Application No. 10170884.0 filed on Jul. 27, 2010 with the European Patent Office.
The present disclosure generally relates to the field of very-large-scale integration design process, and specifically to the assessment of the printability of a layout.
Design Rule Check (DRC) is the first step in the modern very-large-scale integration (VLSI) design process and it uses a large set of rules to eliminate non-printable design patterns from a layout. The DRC applies a set of heuristic design rules that preclude certain design patterns from the design space, and the design rules separate the VLSI design process from the manufacturing process. The DRC creation process is a legacy of pre-100 nm VLSI design era, when a relatively small and simple set of rules could be followed by the layout designers, effectively reducing the risk of low manufacturing yield. Even after substantial extension of the rule set for the sub-100 nm technology nodes, the DRC strategy does not provide satisfactory yield during manufacturability and the design must be revisited multiple times before it reaches production stage.
At the same time, the requirements resulting from the optical properties of the printing process drive the rapid escalation of the number and complexity of the DCR rules. Indeed, creating DRC rules requires a labor-intensive, collaborative effort at the early stage of each technology node. In spite of that effort, the archaic principles driving the creation and use of DRC in combination with the growing complexity of the job at hand cause that i) DRC check pronounces as printable patterns that do not print reliably, and ii) patterns that are valuable from the design perspective and print correctly are erroneously banned by the DRC process. In other terms, false positive and false negative can result of the DRC process.
In order to bypass these problems, solutions have been developed. For instance, it has been proposed to drastically reduce the number of patterns in order to restrict the design space to those shapes and constructs that are guaranteed to be printable. A similar approach, which postulates radical layout regularization for 32 nm technology node, is referred to as prescriptive layout design. In other approach, a semi-automatic generation of new DRC rules (referred to as DRC Plus) has been proposed. The DRC Plus rules are created through identification of classes of design patterns that are likely to cause printability errors. Those patterns are forbidden and removed from the design space, which is a conceptually similar to the prescriptive design principle. However, the application of the DRC Plus may still eliminate perfectly printable patterns.
However, DRC has several drawbacks: DRC is slow, labor-intensive, ad-hoc, inaccurate and excessively restrictive. More precisely, the current DRC process suffers from the following problems:
1. The process is generating a very large number of rules, which also tend to be excessively conservative to avoid yield problems in manufacturing.
2. The complexity and the number of the DRC rules make it a nontransparent, restrictive and suboptimal tool, which prohibits many shapes that actually can be printed.
3. The rules are frequently linked to particular printing problems encountered rather than to the physical phenomena that occur during printing. This fact, in conjunction with the large number of existing rules, creates a situation where rules can be partially redundant and overly restrictive.
4. The number of rules makes tracing of the dependencies between the new rules and the existing ones very hard.
5. The process is not scalable to new technology nodes: it is not obvious if and which of the old rules should hold in the new technology node, and new rules must be added via labor-expensive non-automated error analysis, and rule design.
Thus, according to the limitations of the existing solution shortly discussed above, there is a need for replacing the inefficient set of design rules with a new printability check process able to produce fast, accurate, autonomous printability prediction for lithography, preferably in new technology nodes (e.g. 22 nm, 15 nm).